1. Technical Field
The embodiment described herein relates to a semiconductor memory apparatus and, more particularly, to a voltage pump circuit and a semiconductor memory apparatus using the same.
2. Related Art
After a semiconductor memory chip is fabricated on a wafer, it is checked whether or not the corresponding chip is usable through a test. At this time, when a failure occurs in a memory cell array due to variables during a process, impurities, etc., a redundancy cell is added to the memory chip in order to substitute another cell for the cell that has failed.
However, when excessive failures occur in the cell array, the cell that has failed cannot be substituted by the redundancy cell, thus, the corresponding chip is discarded.
In this case, usable memory cells in the discarded chip are also discarded, such that resources are wasted. Therefore, recently, the usable memory cells are packaged to be used with a capacity smaller than an existing designed capacity, for example, half density.
FIG. 1 is a configuration diagram of a conventional memory chip.
When the capacity of the memory chip is, for example, 2 Gb, the memory chip has a first memory block 20 of 1 GB above the center of the chip and a second memory block 30 of 1 GB below the center of the chip. In addition, the first and second memory blocks 20 and 30 are divided into first and second right memory matrixes 22, 34, ‘M_R’ and first and second left memory matrixes 24, 32, ‘M_L’, respectively.
In the memory chip, for example, it is assumed that excessive defective cells exist in the first and second right memory matrixes 22 and 34. Even in this case, since the first and second left memory matrixes 24 and 32 are usable, the corresponding memory chip may be shipped by being packaged into a 1 GB memory chip.
Meanwhile, a voltage pump circuit that supplies a high voltage to a circuit in the memory chip exists in a semiconductor memory chip for an operation to require a voltage higher than an external supply voltage.
FIG. 2 is a configuration diagram of a conventional voltage pump circuit.
As shown in the figure, the voltage pump circuit 40 can include a voltage detection unit 42 that determines a level of a pumping voltage ‘VPP’ and outputs a pumping enable signal ‘PUMP_EN’, and an oscillation unit 44 that outputs an oscillation signal ‘OSC’ when the pumping enable signal ‘PUMP_EN’ is enabled. Further, the voltage pump circuit 40 can include a sequential generation unit 46 that outputs a driving signal ‘OSCx’ (x is a natural number in the range of 1 to n) in accordance with the output signal of the oscillation unit 44 and a pumping unit 48 including a plurality of pumps that are sequentially driven in accordance with the driving signal ‘OSCx’ outputted from the sequential generating unit 46 to output the pumping voltage ‘VPP’ by boosting an external supply voltage ‘VDD’.
As such, the pumping unit 48 includes the plurality of pumps and the number of pumps is determined in accordance with the capacity of the memory chip. Accordingly, in the case of the memory chip initially designed to have 2 GB, the pumping unit 48 may include, for example, 12 pumps.
However, when the memory chip designed to have 2 GB is packaged with the half density and shipped as 1 GB, many pumps that are not suitable to operate a 1 GB memory chip operate.
That is, the pumps are unnecessarily driven, such that current consumption of the memory apparatus increases.